CP2201 datasheet(96/108 Pages) SILABS

96 / 108 page

CP2200/1

Rev. 1.0

16. Parallel Interface

The CP2200/1 has an 8-bit parallel host interface used to access the direct registers on the device. The parallel

interface supports multiplexed or non-multiplexed operation using the Intel® or Motorola® bus format. The MUXEN

pin can be driven high to place the device in multiplexed operation or driven low to select non-multiplexed

operation. The MOTEN pin can be driven high to place the device in Motorola bus format or driven low to place the

device in Intel bus format.

Notes:

1. The CP2201 (28-pin package) can only be used in multiplexed mode.

2. The PCB traces connecting RD, WR, CS, ALE, and all address and data lines should be matched such that the

propagation delay does not vary by more than 5ns between any two signals.

A parallel interface read or write operation typically requires 260 ns (non-multiplexed) or 300 ns (multiplexed) to

transfer one byte of data. If back-to-back operations are scheduled on a non-multiplexed bus, data rates up to

30 Mbps can be achieved. Tables 26 through 29 provide detailed information about bus timing in each mode.

16.1. Non-Multiplexed Intel Format

Figure 22. Nonmuxed Intel READ

Valid Address

VD2

HOLD

VD1

A[7:0]

D[7:0]

Valid Data

AHR

Notes:

1. CS must be asserted with or before RD.

2. WR must remain de-asserted during a READ.

Valid Address

HOLD

A[7:0]

D[7:0]

Valid Data

AHW

Notes:

1. CS must be asserted with or before WR.

2. RD must remain de-asserted during a WRITE.

CP2201 Datasheet(PDF) 96 Page - Silicon Laboratories