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CP2201 Datasheet(PDF) 72 Page - Silicon Laboratories |
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CP2201 Datasheet(HTML) 72 Page - Silicon Laboratories |
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72 / 108 page  CP2200/1 72 Rev. 1.0 Register 58. RXFIFOSTA: Receive FIFO Status Register This register is set by hardware and is valid after an RX FIFO Full Interrupt is generated or if TLBVALID equals 0xFF. Bits 7–2: UNUSED. Read = 000000b, Write = don’t care. Bits 1–0: FIFOSTA[1:0]: Receive FIFO Status 00: Initial Value—No information. 01: The last packet successfully received used all available free space in the buffer. 10: The last packet successfully received was the 8th packet in the receive buffer. There is free space remaining in the receive buffer; however, the maximum number of packets in the buffer has been reached. Any future packets received will cause overflow. Note: Receiving an unsuccessful 9th packet will cause overflow. 11: The last packet successfully received was the eighth packet in the receive buffer and used all available free space in the buffer. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value — — — — — — FIFOSTA1 FIFOSTA0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x5B |
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