CP2201 datasheet(39/108 Pages) SILABS

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CP2200/1

Rev. 1.0

9.2. Power-fail

When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will

drive the /RST pin low and return the CP2200/1 to the reset state. When VDD returns to a level above VRST, the

CP2200/1 will be released from the reset state as shown in Figure 14.

The power supply monitor circuit (VDD Monitor) is enabled and selected as a reset source by hardware following

every power-on reset. To prevent the device from being held in reset when VDD drops below VRST, the VDD Monitor

may be deselected as a reset source (see RSTEN on page 42) and disabled (see VDMCN on page 39). It is

recommended to leave the VDD Monitor enabled and selected as a reset source at all times.

9.3. Oscillator-Fail Reset

If the system clock derived from the oscillator fails for any reason after oscillator initialization is complete, the reset

circuitry will drive the /RST pin low and return the CP2200/1 to the reset state. The CP2200/1 will remain in the

reset state for approximately 1 ms then exit the reset state in the same manner as that for the power-on reset.

9.4. External Pin Reset

The external /RST pin provides a means for external circuitry to force the CP2200/1 into a reset state. Asserting the

/RST pin low will cause the CP2200/1 to enter the reset state. It is recommended to provide an external pull-up

and/or decoupling capacitor of the /RST pin to avoid erroneous noise-induced resets. The CP2200/1 will exit the

reset state approximately 4 µs after a logic high is detected on /RST.

Bit 7:

VDMEN: VDD Monitor Enable

This bit can be used to disable or enable the VDD Monitor Circuit. Note: The VDD Monitor circuit is

enabled and selected as a reset source following every power-on reset. If the VDD Monitor is

disabled and then reenabled during device operation, it must be allowed to stabilize before it is

selected as a reset source. Selecting the VDD Monitor as a reset source before it has stabilized will

generate a system reset. See Table 13 on page 42 for the minimum VDD Monitor turn-on time.

0: VDD Monitor Disabled.

1: VDD Monitor Enabled.

Bit6:

VDDSTAT: VDD Status

This bit indicates the current power supply status (VDD Monitor output).

0: VDD voltage is at or below the VDD Monitor threshold.

1: VDD voltage is above the VDD Monitor threshold.

Bits 5–0: RESERVED. Read = varies; Write = don’t care.

R/W

RRR

Reset Value

VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Address:

0x13

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