CP2201 datasheet(18/108 Pages) SILABS

18 / 108 page

CP2200/1

Rev. 1.0

6. Functional Description

6.1. Overview

In most systems, the CP2200/1 is used for transmitting and receiving Ethernet packets, non-volatile data storage,

and controlling Link and Activity LEDs. The device is controlled using direct and indirect internal registers

accessible through the parallel host interface. All digital pins on the device are 5 V tolerant.

6.2. Reset Initialization

After every CP2200/1 reset, the following initialization procedure is recommended to ensure proper device

operation:

Step 1: Wait for the reset pin to rise. This step takes the longest during a power-on reset.

Step 2: Wait for Oscillator Initialization to complete. The host processor will receive notification through the

interrupt request signal once the oscillator has stabilized.

Step 3: Wait for Self Initialization to complete. The INT0 interrupt status register on page 31 should be

checked to determine when Self Initialization completes.

Step 4: Disable interrupts (using INT0EN and INT1EN on page 33 and page 36) for events that will not be

monitored or handled by the host processor. By default, all interrupts are enabled after every reset.

Step 5: Initialize the physical layer. See “15.7. Initializing the Physical Layer” on page 90 for a detailed

physical layer initialization procedure.

Step 6: Enable the desired Activity, Link, or Activity/Link LEDs using the IOPWR register on page 45.

Step 7: Initialize the media access controller (MAC). See “14.1. Initializing the MAC” on page 78 for a

detailed MAC initialization procedure.

Step 8: Configure the receive filter. See “12.4. Initializing the Receive Buffer, Filter and Hash Table” on

page 59 for a detailed initialization procedure.

Step 9: The CP2200/1 is ready to transmit and receive packets.

6.3. Interrupt Request Signal

The CP2200/1 has an interrupt request signal (INT) that can be used to notify the host processor of pending

interrupts. The INT signal is asserted upon detection of any enabled interrupt event. Host processors that cannot

dedicate a port pin to the INT signal can periodically poll the interrupt status registers to see if any interrupt

generating events have occurred. If the /INT signal is not used, pending interrupts such a Receive FIFO Full must

still be serviced.

The 14 interrupt sources are listed below. Interrupts are enabled on reset and can be disabled by software.

Pending interrupts can be cleared (allowing the INT signal to de-assert) by reading the self-clearing interrupt

registers. See “8. Interrupt Sources” on page 30 for a complete description of the CP2200/1 interrupts.

End of Packet Reached

Packet Received

Receive FIFO Empty

“Wake-on-LAN” Wakeup Event

Receive FIFO Full

Link Status Changed

Oscillator Initialization Complete

Jabber Detected

Self Initialization Complete

Auto-Negotiation Failed

Flash Write/Erase Complete

Remote Fault Notification

Packet Transmitted

Auto-Negotiation Complete

CP2201 Datasheet(PDF) 18 Page - Silicon Laboratories

CP2201 Datasheet(HTML) 18 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL