RC522 datasheet(19/109 Pages) NXP

19 / 109 page

112132

Product data sheet

Rev. 3.2 — 22 May 2007

19 of 109

NXP Semiconductors

MFRC522

Contactless Reader IC

9.2.1.8

Status1Reg

Contains status bits of the CRC, Interrupt and FIFO buffer.

Table 21:

Status1Reg register (address 07h); reset value: 21h

Bit

Symbol

CRCOk

CRCReady

IRq

TRunning

HiAlert

LoAlert

Access

Rights

RFU

Table 22:

Description of Status1Reg bits

Bit

Symbol

Description

Reserved for future use.

CRCOk

Set to logic 1, if the CRC result is zero. For data transmission and

reception the bit CRCOk is undefined (use CRCErr in register

ErrorReg). CRCOk indicates the status of the CRC co-processor,

during calculation the value changes to logic 0, when the calculation is

done correctly, the value changes to logic 1.

CRCReady

Set to logic 1, when the CRC calculation has finished. This bit is only

valid for the CRC co-processor calculation using the command

CalcCRC.

IRq

This bit shows, if any interrupt source requests attention (with respect

to the setting of the interrupt enable bits, see register CommIEnReg

and DivIEnReg).

TRunning

Set to logic 1, if the MFRC522’s timer unit is running, e.g. the timer will

decrement the TCounterValReg with the next timer clock.

Remark: In the gated mode the bit TRunning is set to logic 1, when

the timer is enabled by the register bits. This bit is not

influenced by the gated signal.

Reserved for future use.

HiAlert

Set to logic 1, when the number of bytes stored in the FIFO buffer

fulfils the following equation:

Example:

FIFOLength = 60, WaterLevel = 4

→ HiAlert = 1

FIFOLength = 59, WaterLevel = 4

→ HiAlert = 0

LoAlert

Set to logic 1, when the number of bytes stored in the FIFO buffer

fulfils the following equation:

Example:

FIFOLength = 4, WaterLevel = 4

→ LoAlert = 1

FIFOLength = 5, WaterLevel = 4

→ LoAlert = 0

HiAlert

FIFOLength

–

)

(

WaterLevel

≤

LoAlert

FIFOLength

WaterLevel

≤

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