Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

HD6433713 Datasheet(PDF) 34 Page - Renesas Technology Corp

Part # HD6433713
Description  single-chip microcontrollers
PDF  324 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6433713 Datasheet(HTML) 34 Page - Renesas Technology Corp

Back Button HD6433713 Datasheet HTML 30Page - Renesas Technology Corp HD6433713 Datasheet HTML 31Page - Renesas Technology Corp HD6433713 Datasheet HTML 32Page - Renesas Technology Corp HD6433713 Datasheet HTML 33Page - Renesas Technology Corp HD6433713 Datasheet HTML 34Page - Renesas Technology Corp HD6433713 Datasheet HTML 35Page - Renesas Technology Corp HD6433713 Datasheet HTML 36Page - Renesas Technology Corp HD6433713 Datasheet HTML 37Page - Renesas Technology Corp HD6433713 Datasheet HTML 38Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 34 / 324 page
background image
2.4 Addressing Modes
2.4.1 Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a
subset of these addressing modes.
Table 2-1 Addressing Modes
No.
Address Modes
Symbol
1
Register direct
Rn
2
Register indirect
@Rn
3
Register indirect with displacement
@(d:16, Rn)
4
Register indirect with post-increment
@Rn+
Register indirect with pre-decrement
@–Rn
5
Absolute address
@aa:8 or @aa:16
6
Immediate
#xx:8 or #xx:16
7
Program-counter relative
@(d:8, PC)
8
Memory indirect
@@aa:8
1.
Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits
× 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
2.
Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
3.
Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word
(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting
address must be even.
23



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com