| Electronic Components Datasheet Search |
|
HD6433713 Datasheet(PDF) 94 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD6433713 Datasheet(HTML) 94 Page - Renesas Technology Corp |
|
94 / 324 page ![]() 3.4 System Control Registers Table 3-7 shows how the system control registers (SYSCR1 and SYSCR2) are configured. These two registers are used to control the power-down modes. Table 3-7 Register Configuration Name Abbreviation R/W Initial Value Address System control register 1 SYSCR1 R/W H'00 H'FFF0 System control register 2 SYSCR2 R/W H'F4 H'FFF1 3.4.1 System Control Register 1 (SYSCR1) Note: * Write is enabled only in active mode. SYSCR1 is an 8-bit read/write register for control of power-down modes. Bit 7: Standby (SSBY) This bit designates transition to standby mode. When standby mode is cleared by an external interrupt and the system goes to active mode, this bit remains set to 1. It must be cleared by writing a 0. Writing is possible only in active mode. Bit 7 SSBY Explanation 0 When a SLEEP instruction is executed, a transition is made to sleep (initial value) mode. 1 When a SLEEP instruction is executed, a transition is made to standby mode or watch mode. Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W 0 — 0 — 2 — 0 R/W 1 — 0 — * 83 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |