HD6433713 datasheet(80/324 Pages) RENESAS

80 / 324 page

The following operations take place when an interrupt occurs.

When an interrupt is requested by external interrupt pin input or by a peripheral module, an

interrupt request signal is sent to the interrupt controller.

When the interrupt controller receives an interrupt request signal, it sets the interrupt request

flag.

From among the interrupts for which the corresponding interrupt enable bit is also set to 1,

the interrupt controller selects the interrupt request with the highest priority and holds the

others pending. (See table 3-2.)

The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request

is accepted; if the I bit is 1, the interrupt request is held pending.

If the interrupt is accepted, after processing of the current instruction is completed, both PC

and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4.

The PC value pushed onto the stack is the address of the first instruction to be executed upon

return from interrupt handling.

The I bit of CCR is set to 1, masking all further interrupts.

A vector address is generated for the accepted interrupt, and the contents of that address are

read and loaded into PC. Program execution then resumes from the address indicated in PC.

Note: No interrupt detection takes place immediately after completion of ORC, ANDC, XORC,

or LDC instructions.

HD6433713 Datasheet(PDF) 80 Page - Renesas Technology Corp