HD6433713 datasheet(91/324 Pages) RENESAS

91 / 324 page

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Clearing watch mode

Watch mode is cleared by a time-base interrupt from timer A, by an IRQ0 interrupt, or by

input at the

RES pin.

— Clearing by timer A time-base interrupt or IRQ0 interrupt

When timer A overflows or an IRQ0 interrupt signal is input, if the LSON bit in system

control register 1 (SYSCR1) is cleared to 0, the clock pulse generator starts. After the time

set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed, a stable clock

signal is supplied to the entire chip, watch mode is cleared, and interrupt exception

handling starts. If LSON = 1, the system goes to subactive mode.

In watch mode, the subclock (

SUB) is prescaled to generate a clock signal which is

supplied to timer A. Timer A operates as a time base.

Before the transition to watch mode, other external interrupts should be disabled. Watch

mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the

particular interrupt is disabled in the interrupt enable register.

— Clearing by

RES input

When the

RES pin goes low, the clock pulse generator starts and watch mode is cleared.

After the pulse generator output has stabilized, if the

RES pin is driven high, the CPU

starts reset exception handling.

Since clock signals are supplied to the entire chip as soon as the clock pulse generator

starts functioning, the

RES pin should be kept at the low level until the pulse generator

output stabilizes.

Subactive mode

Operation in subactive mode is described below.

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Transition to subactive mode

Subactive mode is entered from watch mode if the LSON bit in system control register 1

(SYSCR1) is set to 1 at the time of a timer A time-base interrupt or IRQ0 interrupt request.

In subactive mode, the CPU operates in synchronization with the subclock (

SUB). The on-

chip peripheral modules halt operation, except for the time base function of timer A. Output

from the on-chip peripheral modules is reset; but as long as a minimum required voltage is

applied, the contents of the internal registers of the on-chip peripheral modules are retained.

Standard I/O ports go to the high-impedance state. In high-voltage ports, the PMOS buffer

transistors are switched off.

HD6433713 Datasheet(PDF) 91 Page - Renesas Technology Corp