HD6433713 datasheet(89/324 Pages) RENESAS

89 / 324 page

Sleep mode

Operation in sleep mode is described below.

•

Transition to sleep mode

The system goes from active mode to sleep mode when a SLEEP instruction is executed while

the SSBY bit in system control register 1 (SYSCR1) is cleared to 0. In this mode CPU

operation is halted but the register, RAM, and port contents are retained. The clock pulse

generator operates, as do external interrupts (IRQ1 and IRQ0) and timer A.

•

Clearing sleep mode

Sleep mode is cleared by an interrupt (IRQ1, IRQ0, or timer A) or by input at the RES pin.

— Clearing by interrupt (IRQ1, IRQ0, or timer A)

When an IRQ1, IRQ0, or timer A interrupt is requested, sleep mode is cleared and interrupt

exception handling starts. Sleep mode is not cleared if the I bit in the condition code

Before transition to sleep mode, other interrupts should be disabled.

— Clearing by

RES input

When the

RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.

Standby mode

Operation in standby mode is described below.

•

Transition to standby mode

The system goes from active mode to standby mode when a SLEEP instruction is executed

while the SSBY bit in system control register 1 (SYSCR1) is set to 1 and bit TMA3 in timer

mode register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so

the CPU and on-chip peripheral modules stop functioning. As long as a minimum required

voltage is applied, the CPU register contents and data in the on-chip RAM will be retained.

Standard I/O ports go to the high-impedance state. In high-voltage ports, the PMOS buffer

transistors are switched off.

HD6433713 Datasheet(PDF) 89 Page - Renesas Technology Corp