HD6433713 datasheet(76/324 Pages) RENESAS

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Bit 5: Direct transfer interrupt request (IRRDT)

Bits 5

IRRDT

Description

No direct transfer interrupt request.

(initial value)

Setting conditions: In subactive mode, when the system control register 2

(SYSCR2) DTON bit = 1, the system control register 1 (SYSCR1) LSON bit = 0,

and the interrupt enable register 2 (IENR2) IENDT bit = 1, execution of a SLEEP

instruction results in direct transfer to active mode via watch mode. During this

process a direct transfer interrupt is requested and the IRRDT flag is set to 1.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not

automatically cleared when an interrupt is accepted.)

Bits 4 to 0: Timer E to A interrupt request (IRRTE to IRRTA)

Bits 4 to 0

IRRTE to IRRTA

Description

No overflow interrupt request from the corresponding timer

(initial value)

(E to A).

Setting conditions: When a timer E to A overflow interrupt is requested, the

corresponding flag (IRRTE to IRRTA ) is set to 1.

Clearing method: Cleared when software writes 0 in the flag. (The flag is

not automatically cleared when an interrupt is accepted.)

Interrupt request register 3 (IRR3)

Note: * Only 0 can be written, to clear the flag.

Bit 7: A/D conversion complete interrupt request (IRRAD)

Bit 7

IRRAD

Description

No A/D converter interrupt request.

(initial value)

Setting conditions: When the A/D converter completes A/D conversion, an interrupt

is requested and the IRRAD flag is set to 1.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not

automatically cleared when an interrupt is accepted.)

Bit

Initial value

Read/Write

IRRAD

R/W

IRRKS

R/W

—

IRRS1

R/W

—

IRRS2

R/W

HD6433713 Datasheet(PDF) 76 Page - Renesas Technology Corp

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