HD6433713 datasheet(95/324 Pages) RENESAS

95 / 324 page

Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0)

When a mode in which the system clock is stopped (standby, watch, or subactive mode) is cleared,

the system waits for stable clock operation for a time set in these bits. The designation should be

made according to the clock frequency so that the waiting time is at least 10 ms.

Bit 6

Bit 5

Bit 4

STS2

STS1

STS0

Explanation

Wait time = 8,192

states. (initial value)

Wait time = 16,384 states.

Wait time = 32,768 states.

Wait time = 65,536 states.

Wait time = 131,072 states.

Note: * Don’t care.

Bit 3: Low speed on flag (LSON)

This bit chooses the system clock (

φ) or subclock (φ

SUB) as the CPU operating clock when watch

mode is cleared. Since this relates to the transitions between operation modes, this bit functions in

combination with other control bits and interrupt input.

Bit 3

LSON

Explanation

The CPU operates on the system clock (

φ).

(initial value)

The CPU operates on the subclock (

φSUB).

Bit 2: Reserved bit

This bit is reserved, but it can be written and read.

Bits 1 and 0: Reserved bits

These bits are reserved; they always read 0, and cannot be modified.

HD6433713 Datasheet(PDF) 95 Page - Renesas Technology Corp