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HD6433713 Datasheet(PDF) 72 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 72 Page - Renesas Technology Corp |
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72 / 324 page ![]() Bit 1: IRQ1 pin input edge select (IEG1) Bit 1 IEG1 Description 0 Falling edge of IRQ1 pin input is detected. (initial value) 1 Rising edge of IRQ1 pin input is detected. Bit 0: IRQ0 pin input edge select (IEG0) Bit 0 IEG0 Description 0 Falling edge of IRQ0 pin input is detected. (initial value) 1 Rising edge of IRQ0 pin input is detected. 3. Interrupt enable register 1 (IENR1) IENR1 is an 8-bit read/write register that enables or disables external interrupts. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they always read 1, and cannot be modified. Bits 5 and 4: IRQ5 and IRQ4 interrupt enable (IEN5 and IEN4) Bits 5 and 4 IEN5, IEN4 Description 0 Disables interrupt requests by IRRI5 and IRRI4. (initial value) 1 Enables interrupt requests by IRRI5 and IRRI4. Bits 3 and 2: Reserved bits Bits 3 and 2 are reserved, but they can be written and read. Bits 1 and 0: IRQ1 and IRQ0 interrupt enable (IEN1 and IEN0) Bits 1 and 0 IEN1, IEN0 Description 0 Disables interrupt requests by IRRI1 and IRRI0. (initial value) 1 Enables interrupt requests by IRRI1 and IRRI0. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 IEN5 0 R/W 4 IEN4 0 R/W 3 — 0 R/W 0 IEN0 0 R/W 2 — 0 R/W 1 IEN1 0 R/W 61 |
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