HD6433713 datasheet(92/324 Pages) RENESAS

92 / 324 page

•

Clearing subactive mode

Subactive mode is cleared by a SLEEP instruction or by input at the

RES pin.

— Clearing by SLEEP instruction

When a SLEEP instruction is executed in subactive mode, subactive mode is cleared.

If the DTON bit of system control register 2 (SYSCR2) is cleared to 0 when the SLEEP

instruction is executed, the system goes to watch mode. If DTON = 1 and

LSON = 0, a direct transfer interrupt is requested and the clock pulse generator starts.

After the time set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed,

a stable clock signal is supplied to the entire chip, and the system goes to active mode.

Before the transition to active mode, other interrupts should be disabled. The direct

transfer from subactive mode to active mode does not take place if the I bit in the condition

code register (CCR) is set to 1 or the direct transfer interrupt is disabled in the interrupt

enable register.

— Clearing by

RES input

When the

RES pin goes low, the clock pulse generator starts and subactive mode is

cleared. After the pulse generator output has stabilized, if the

RES pin is driven high, the

CPU starts reset exception handling.

Since clock signals are supplied to the entire chip as soon as the clock pulse generator

starts functioning, the

RES pin should be kept at the low level until the pulse generator

output stabilizes.

HD6433713 Datasheet(PDF) 92 Page - Renesas Technology Corp