HD6433713 datasheet(78/324 Pages) RENESAS

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When an IRQ5, IRQ4, IRQ1, or IRQ0 interrupt request is accepted, the I bit is set to 1. The order

of priority is from IRQ0 (high) to IRQ5 (low). For details see table 3-2.

A noise canceller function can be selected for IRQ0 interrupts, in which case a noise cancellation

circuit samples the IRQ0 input every 256 states. If two consecutive sampling results do not match,

noise is assumed and the request is not accepted.

3.2.5 Internal Interrupts

There are ten internal interrupts that can be requested by the on-chip peripheral modules. These

interrupts can be masked (held pending) by setting the I bit in CCR to 1. When an internal

interrupt request is accepted and the interrupt exception handling sequence is executed, the I bit is

set to 1. For the order of priority of interrupts from on-chip peripheral modules, see table 3-2.

3.2.6 Interrupt Operations

Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the

interrupt controller, while figure 3-3 shows the flow up to interrupt acceptance.

Figure 3-2 Block Diagram of Interrupt Controller

Interrupt controller

Interrupt

request

CCR (CPU)

IRQ , IQR , IRQ , and

IRQ interrupt request

flags and internal

interrupt request flags

IRQ , IQR , IRQ , and

IRQ interrupt enable

bits and internal

interrupt enable bits

HD6433713 Datasheet(PDF) 78 Page - Renesas Technology Corp