HD6433713 datasheet(90/324 Pages) RENESAS

90 / 324 page

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Clearing standby mode

Standby mode is cleared by an external interrupt (IRQ1, IRQ0) or by input at the RES pin.

— Clearing by interrupt (IRQ1, IRQ0)

When an IRQ1 or IRQ0 interrupt signal is input, the clock pulse generator starts. After the

time set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed, a stable

clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception

handling starts. Before the transition to standby mode, other interrupts should be disabled.

Standby mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or

the particular interrupt is disabled in the interrupt enable register.

— Clearing by

RES input

When the

RES pin goes low, the clock pulse generator starts and standby mode is cleared.

After the pulse generator output has stabilized, if the

RES pin is driven high, the CPU

starts reset exception handling.

Since clock signals are supplied to the entire chip as soon as the clock pulse generator

starts functioning, the

RES pin should be kept at the low level until the pulse generator

output stabilizes.

Watch mode

Operation in watch mode is described below.

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Transition to watch mode

From active mode, watch mode is entered when a SLEEP instruction is executed while the

SSBY bit in system control register 1 (SYSCR1) is set to 1 and bit TMA3 in timer mode

instruction is executed while the DTON bit in system control register 2 (SYSCR2) is cleared

to 0.

In watch mode, operation of the system clock pulse generator and of on-chip peripheral

modules is halted, except for the time-base function of timer A. Output from the on-chip

peripheral modules is reset; but as long as a minimum required voltage is applied, the contents

of the internal registers of the CPU and on-chip peripheral modules, and the on-chip RAM

contents, are retained.

HD6433713 Datasheet(PDF) 90 Page - Renesas Technology Corp