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HD6433713 Datasheet(PDF) 81 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 81 Page - Renesas Technology Corp |
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81 / 324 page ![]() Figure 3-4 Stack State after Completion of Interrupt Exception Handling Figure 3-5 shows a typical interrupt sequence. Contents saved to stack SP (R7) SP – 1 SP – 2 SP – 3 SP – 4 Stack area SP + 4 SP + 3 SP + 2 SP + 1 SP (R7) Even address Prior to start of interrupt exception handling After completion of interrupt exception handling Notation: PCH: PCL: CCR: SP: Upper 8 bits of program counter (PC) Lower 8 bits of program counter (PC) Condition code register Stack pointer * Ignored on return from interrupt. Notes: 1. 2. CCR CCR* PCH PCL PC shows the address of the first instruction to be executed upon return from the interrupt. Saving and restoring of register contents must always be done in word size, and must start from an even-numbered address. 70 |
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