HD6433713 datasheet(84/324 Pages) RENESAS

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3.2.9 Valid Interrupts in Each Mode

Table 3-5 shows the valid interrupts in each mode. For details of the modes, see 3.3, System

Modes.

Table 3-5 Valid Interrupts in Each Mode

Mode

Interrupt

Active

Sleep

Standby

Watch

Subactive

IRQ0

rrrrr

IRQ1

rrr

××

IRQ4

××××

IRQ5

××××

Key scan

××××

Timer A overflow

Timer B overflow

××××

Timer C overflow

××××

Timer D overflow

××××

Timer E overflow

××××

Direct transfer

××××∆

SCI1 transfer complete or error

××××

SCI2 transfer complete or error

××××

A/D conversion end

××××

Note: The above table does not include interrupts occurring during a mode transition.

Notation:

: When an interrupt request flag is set, interrupt exception handling is started if the I bit = 0 in

CCR and the interrupt enable bit = 1 for that interrupt. In sleep mode, standby mode, and

watch mode, a mode transition takes place before interrupt exception handling starts.

∆: When a SLEEP instruction is executed while the DTON bit = 1 and the LSON bit = 0, first a

transition is made to watch mode and the interrupt request flag is set in synchronization with

the subclock. When the interrupt request flag is set, if the interrupt enable flag = 1 for that

interrupt and the I bit = 0 in CCR, a transition is made to active mode and interrupt exception

handling starts.

×: The interrupt request flag is not set, and no mode transition occurs.

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