HD6433713 datasheet(75/324 Pages) RENESAS

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Bits 5 and 4: IRQ5 and IRQ4 interrupt request (IRRI5 and IRRI4)

Bits 5 and 4

IRRI5, IRRI4

Description

No interrupt request from the corresponding pin (IRQ5 or IRQ4). (initial value)

Setting condition: Set when the corresponding pin (IRQ5 or IRQ4) is

designated for interrupt input in PMR1 and the designated edge is input.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not

automatically cleared when an interrupt is accepted.)

Bits 3 and 2: Reserved bits

Bits 3 and 2 are reserved; they always read 0, and cannot be modified.

Bits 1 and 0: IRQ1 and IRQ0 interrupt request (IRRI1 and IRRI0)

Bits 1 and 0

IRRI1, IRRI0

Description

No interrupt request from the corresponding pin (IRQ1 or IRQ0). (initial value)

Setting condition: Set when the corresponding pin (IRQ1 or IRQ0) is

designated for interrupt input in PMR1 and the designated edge is input.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not

automatically cleared when an interrupt is accepted.)

Interrupt request register 2 (IRR2)

Note: * Only 0 can be written, to clear the flag.

IRR2 is an 8-bit read/write register with flags that are set to 1 when a direct transfer interrupt or

timer A to E overflow interrupt is requested.

Bits 7 and 6: Reserved bits

Bits 7 and 6 are reserved; they always read 0, and only 0 may be written.

Bit

Initial value

Read/Write

—

IRRDT

R/W

IRRTE

R/W

IRRTD

R/W

IRRTA

R/W

IRRTC

R/W

IRRTB

R/W

HD6433713 Datasheet(PDF) 75 Page - Renesas Technology Corp

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