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HD6433713 Datasheet(PDF) 93 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 93 Page - Renesas Technology Corp |
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93 / 324 page  3.3.3 Application Notes 1. In order to ensure sufficient time for the clock pulse generator to reach stable operation after clearing of standby mode or watch mode, or after a direct transfer from subactive to active mode, bits STS2 to STS0 in system control register 1 (SYSCR1) should be set as follows. • When a ceramic oscillator is used Set bits STS2 to STS0 for a waiting time of at least 10 ms (see figure 3-9). For details, see 3.4.1, System Control Register 1 (SYSCR1). • When an external clock is used Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set. Figure 3-9 Waiting Time 2. To make a transition from subactive mode to active mode, the LSON bit in SYSCR1 should be cleared to 0 and the DTON bit in system control register 2 (SYSCR2) should be set to 1. Direct transfer is not possible when the LSON bit = 1. Power-on or standby cleared V t Oscillator stabilization time tr Waiting time ≥10 ms Oscillator waveform 82 |
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