HD6433713 datasheet(87/324 Pages) RENESAS

87 / 324 page

3.3.1 Active Mode

In active mode, the CPU executes instructions in synchronization with the system clock.

3.3.2 Low-Power Operation Mode

The H8/300L CPU supports four low-power operation modes: sleep mode, standby mode, watch

mode, and subactive mode. These modes are described below.

Sleep mode:

Sleep mode is entered by executing a SLEEP instruction while the SSBY bit

in system control register 1 (SYSCR1) is cleared to 0. As soon as the SLEEP

instruction has been executed, the CPU and on-chip peripheral modules halt

operation, except for timer A. The contents of the internal registers of the

CPU and on-chip peripheral modules, as well as the RAM contents, are

retained.

Standby mode:

Standby mode is entered by executing a SLEEP instruction while the SSBY

bit in system control register 1 (SYSCR1) is set to 1 and timer mode register

A (TMA) bit TMA3 = 0. In this mode, the CPU, system clock, and on-chip

peripheral modules halt all operations. Output from the on-chip peripheral

modules is reset; but as long as a minimum required voltage is applied, the

contents of the internal registers of the CPU and on-chip peripheral modules,

as well as the RAM contents, are retained. Standard I/O ports go to the high-

impedance state. In high-voltage ports, the PMOS buffer transistors are

switched off.

Watch mode:

Watch mode is entered by executing a SLEEP instruction while the SSBY bit

in system control register 1 (SYSCR1) is set to 1 and timer mode register A

(TMA) bit TMA3 = 1. In this mode, the CPU, system clock, and on-chip

peripheral modules halt, except for timer A. Output from the on-chip

peripheral modules is reset; but as long as a minimum required voltage is

applied, the contents of the internal registers of the CPU and on-chip

peripheral modules, as well as the RAM contents, are retained. Standard I/O

ports go to the high-impedance state. In high-voltage ports, the PMOS buffer

transistors are switched off.

Subactive mode:

Subactive mode is entered when a time base or IRQ0 interrupt request is

accepted in watch mode while the LSON bit in system control register 1

(SYSCR1) is set to 1. In this mode the CPU operates in synchronization with

the subclock. On-chip peripheral modules halt operation, except for the time-

base function of timer A. Output from the on-chip peripheral modules is

reset; but as long as a minimum required voltage is applied, the contents of the

internal registers of the on-chip peripheral modules are retained. Standard I/O

ports go to the high-impedance state. In high-voltage ports, the PMOS buffer

transistors are switched off.

HD6433713 Datasheet(PDF) 87 Page - Renesas Technology Corp

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