HD6433713 datasheet(96/324 Pages) RENESAS

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3.4.2 System Control Register 2 (SYSCR2)

Note: * Write is enabled only in subactive mode.

SYSCR2 is an 8-bit read/write register for control of direct transfer from subactive mode to active

mode.

Bits 7 to 4: Reserved bits

These bits are reserved; they always read 1, and cannot be modified.

Bit 3: Direct transfer on flag (DTON)

This bit designates whether a transition is made to active mode or to watch mode when a SLEEP

instruction is executed in subactive mode. When transfer to active mode is designated, the

transition takes place via watch mode to allow time for the clock pulse generator to stabilize.

Bit 3

DTON

Explanation

When a SLEEP instruction is executed in subactive mode, a transition is

(initial value)

made to watch mode.

When a SLEEP instruction is executed in subactive mode while the LSON bit in system

control register 1 (SYSCR1) is cleared to 0, a direct transfer interrupt is requested, and

the system goes to active mode via watch mode.

Bit 2: Reserved bit

This bit is reserved; it always reads 1, and cannot be modified.

Bits 1 and 0: Reserved bits

These bits are reserved, but they can be written and read.

Bit

Initial value

Read/Write

—

DTON

—

R/W

—

R/W

HD6433713 Datasheet(PDF) 96 Page - Renesas Technology Corp