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HD6433713 Datasheet(PDF) 58 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 58 Page - Renesas Technology Corp |
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58 / 324 page  2.7 Basic Operation Timing CPU operation is synchronized by a clock ( φ i). φi is either the system clock (φ) generated by the system clock oscillator circuit, or the subclock ( φ SUB) generated by the subclock oscillator circuit. φ i denotes φ in active mode and φSUB in subactive mode. For details, see section 6, Clock Pulse Generators. The period from the rising edge of φ i to the next rising edge is called one state. A memory cycle or bus cycle consists of two states; access to on-chip memory and to on-chip peripheral modules always takes place in two states. 2.7.1 Access to On-Chip Memory (RAM, ROM) Two-state access is employed for on-chip memory. The data bus width is 16 bits, allowing access in byte or word size. Figure 2-14 shows the on-chip memory access cycle. Figure 2-14 On-Chip Memory Access Cycle T1 state Bus cycle T2 state φ Internal address bus Internal read signal Internal data bus (read access) Internal write signal Read data Address Write data Internal data bus (write access) i 47 |
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