HD6433713 datasheet(77/324 Pages) RENESAS

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Bit 6: Key scan interrupt request (IRRKS)

Bit 6

IRRKS

Description

No key scan interrupt request.

(initial value)

Setting conditions: When the VFD controller/driver requests a key scan interrupt,

the IRRKS flag is set to 1.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not

automatically cleared when an interrupt is accepted.)

Bits 5 to 2: Reserved bits

Bits 5 to 2 are reserved; they always read 1, and cannot be modified.

Bits 1 and 0: Serial communication interface 2 and 1 interrupt request (IRRS2, IRRS1)

Bits 1, 0

IRRS2, IRRS1

Description

No transfer complete or error interrupt request by the

(initial value)

corresponding serial communication interface.

Setting conditions: When an interrupt is requested due to transfer complete or

error on serial communication interface 2 or 1, the corresponding flag (IRRS2 or

IRRS1) is set to 1.

Clearing method: Cleared when software writes 0 in the flag. (The flag is not

automatically cleared when an interrupt is accepted.)

3.2.4 External Interrupts

There are four external interrupts, IRQ5, IRQ4, IRQ1, and IRQ0. These interrupts are requested by

means of input signals at pins IRQ5, IRQ4, IRQ1, and IRQ0.

Interrupts IRQ4, IRQ1, and IRQ0 are detected by either rising edge sensing or falling edge

sensing, depending on the settings of bits IEG4, IEG1, and IEG0 in the IRQ edge select register

(IEGR). IRQ5 is detected by falling edge sensing only. In order to enable external interrupt input,

it is first necessary to set the corresponding bit in port mode register 1 (PMR1) to 1.

When the designated edge is input at pins IRQ5, IRQ4, IRQ1, and IRQ0, the corresponding flag in

interrupt request register 1 (IRR1) is set to 1. After the interrupt is accepted, the flag that was set

is not automatically cleared, so the interrupt handling routine must be programmed to clear the

flag to 0. A given interrupt request can be disabled by clearing its interrupt enable bit to 0.

Interrupts IRQ5, IRQ4, IRQ1, and IRQ0 are enabled by setting bits IEN5, IEN4, IEN1, and IEN0

to 1 in interrupt enable register 1. All interrupts can be masked by setting the I bit in CCR to 1.

HD6433713 Datasheet(PDF) 77 Page - Renesas Technology Corp