HD6433713 datasheet(73/324 Pages) RENESAS

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Interrupt enable register 2 (IENR2)

IENR2 is an 8-bit read/write register that enables or disables direct transfer interrupts and timer A

to E overflow interrupts.

Bits 7 and 6: Reserved bits

Bits 7 and 6 are reserved, but they can be written and read.

Bit 5: Direct transfer interrupt enable (IENDT)

Bit 5

IENDT

Description

Disables direct transfer interrupt requests by IRRDT.

(initial value)

Enables interrupt requests by IRRDT.

Bits 4 to 0: Timer E to A interrupt enable (IENTE to IENTA)

Bits 4 to 0

IENTE to IENTA

Description

Disables interrupt requests by IRRTE to IRRTA.

(initial value)

Enables interrupt requests by IRRTE to IRRTA.

Interrupt enable register 3 (IENR3)

IENR3 is an 8-bit read/write register that enables or disables A/D converter, key scan, and serial

communication interface 1 and 2 interrupts.

Bit

Initial value

Read/Write

—

R/W

—

R/W

IENDT

R/W

IENTE

R/W

IENTD

R/W

IENTA

R/W

IENTC

R/W

IENTB

R/W

Bit

Initial value

Read/Write

IENAD

R/W

IENKS

R/W

—

IENS1

R/W

—

IENS2

R/W

HD6433713 Datasheet(PDF) 73 Page - Renesas Technology Corp

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