7630 datasheet(154/238 Pages) RENESAS

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2-88

7630 Group User’s Manual

APPLICATION

2.5 Serial I/O

Control procedure : Figure 2.5.28 shows a control procedure on the transmitting side, and Figure

2.5.29

shows a control procedure on the receiving side.

Fig. 2.5.28 Control procedure on transmitting side [Communication using UART]

RESET

Initialization

UMOD [Address: 002016]

CPUM [Address: 000016]

00000X002

100X101X2

X : These bits are not used in this application.

Please set these bits to “0” or “1” appropriately.

UCON [Address: 002216]

XXXX01002

•

φ = f(XIN) divided by 2 (high-speed mode)

UBRG [Address: 002116]

4 – 1

UCON [Address: 002216], bit 0

• Transmit enable (Start of communication)

UTBR1 [Address: 002416]

Transmission data (9 bits)

• Write 9 bits of transmission data to the Transmit buffer register.

The Transmit shift register shift completion flag is cleared to “0” by

this writing.

USTS [Address: 002316], bit 0?

• Check the shift completion of the Transmit shift register with the

Transmit shift register shift completion flag.

UCON [Address: 002216], bit 2

• Transmit initialization (End of communication)

The Transmit enable bit is cleared to “0”.

The Transmission register empty flag is set to “1”.

The Transmission buffer empty flag is set to “1”.

When the UCTS input level is “L”,

start transmission (Note).

• Transmitting side

• Transfer data format : 1ST-9DATA-2SP

• Transmit initialization

The Transmit enable bit is cleared to “0”.

The Transmission register empty flag is set to “1”.

The Transmission buffer empty flag is set to “1”.

UTBR2 [Address: 002516], bit 0

Note: Controlled by the serial I/O logic.

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