7630 datasheet(152/238 Pages) RENESAS

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2-86

7630 Group User’s Manual

APPLICATION

2.5 Serial I/O

Fig. 2.5.26 Setting of related registers on transmitting side [Communication using UART]

USTS

UART status register [Address: 002316]

Transmission register empty flag :

This flag is set to “1” at transmit shift completed.

Check a completion of transmitting 1-word data with this flag.

Transmission buffer empty flag :

This flag is set to “1” at transfer data from the Transmit buffer

• Transmitting side

CPUM

CPU mode register [Address: 000016]

Internal system clock selection bit :

φ = f(XIN) divided by 2

(high-speed mode)

UMOD

UART mode register [Address: 002016]

Clock divider selection bits :

φ divided by 8

101

Stop bits selection bit : Two stop bits

Parity enable bit : Parity disabled

Word length selection bits : 9 bits

UCON

UART control register [Address: 002216]

Transmit enable bit : Transmit disabled

(Set this bit to “1” at starting communication.)

Receive enable bit : Receive disabled

Transmission initialization bit : Initialize the transmit enable bit and

transmit status register flags.

Receive initialization bit : No action

UBRG

UART baud rate generator [Address: 002116]

Set

Transfer bit rate ! 16 !

V The value p is decided by the Clock divider selection bits (bit 1 and bit 2

of the UART mode register [address: 002016]). Refer to Table 2.5.2.

– 1

Figure 2.5.26 shows a setting of related registers at a transmitting side, and Figure 2.5.27 shows a

setting of related registers at a receiving side.

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