7630 datasheet(148/238 Pages) RENESAS

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2-82

7630 Group User’s Manual

APPLICATION

2.5 Serial I/O

Fig. 2.5.21 Setting of related registers on receiving side [Communication using UART]

USTS

UART status register [Address: 002316]

Receive buffer full flag :

This flag is set to “1” at receive completed.

Check whether the receive data is readable out from the Receive

buffer register with this flag.

• Receiving side

CPUM

CPU mode register [Address: 000016]

Internal system clock selection bit :

φ = f(XIN) divided by 2

(high-speed mode)

UMOD

UART mode register [Address: 002016]

Clock divider selection bits :

φ divided by 8

101

Stop bits selection bit : Two stop bits

Parity enable bit : Parity checking disabled

Word length selection bits : 8 bits

UCON

UART control register [Address: 002216]

Receive enable bit : Receive disabled

(Set this bit to “1” at starting communication.)

Transmit enable bit : Transmit disabled

Transmission initialization bit : No action

Receive initialization bit : Initialize the receive eneble bit and

receive status register flags.

UBRG

UART baud rate generator [Address: 002116]

Set

Transfer bit rate ! 16 !

V The value p is decided by the Clock divider selection bits (bit 1 and bit 2

of the UART mode register [address: 002016]). Refer to Table 2.5.2.

– 1

Receive framing error flag : This flag is set to “1” at framing error detected.

Receive overrun flag : This flag is set to “1” at overrun detected.

Receive error sum flag : This flag is set to “1” at some error detected.

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