7630 datasheet(146/238 Pages) RENESAS

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2-80

7630 Group User’s Manual

APPLICATION

2.5 Serial I/O

Table 2.5.1 shows setting examples of UART baud rate generator (UBRG) values and transfer bit rate

values, Figure 2.5.20 shows a setting of related registers on the transmitting side, and Figure 2.5.21

shows a setting of related registers on the receiving side.

Table 2.5.1 Setting examples of Baud rate generator values and transfer bit rate values

Transfer bit rate BRG count source

φ = 8MHz / 2

φ = 10MHz / 2

(bps) (Note 1)(Note 2)

BRG setting value

Actual time (bps)

BRG setting value

Actual time (bps)

φ/256

12 (0C16)

75.12

15 (0F16)

76.29

150

φ/256

5 (0516)

162.76

7 (0716)

152.58

300

φ/32

25 (1916)

300.48

31 (1F16)

305.17

600

φ/32

12 (0C16)

600.96

15 (0F16)

610.35

1200

φ/32

5 (0516)

1302.08

7 (0716)

1220.70

2400

φ/8

12 (0C16)

2403.84

15 (0F16)

2441.40

4800

φ/8

5 (0516)

5208.33

7 (0716)

4882.81

9600

φ/8

2 (0216)

10416.66

3 (0316)

9765.62

19200

12 (0C16)

19230.76

15 (0F16)

19531.25

31250

7 (0716)

31250.00

9 (0916)

31250.00

62500

3 (0316)

62500.00

4 (0416)

62500.00

76800

2 (0216)

83333.33

3 (0316)

78125.00

Notes 1: Equation of transfer bit rate

Transfer bit rate (bps) =

(BRG setting value + 1) ! 16 !

Notes 2: BRG count source (

φ/pV) is selected by the Clock divider selection bits (bit 1 and 2 of the UART

mode register [Address: 002016]).

V The Value p is decided by the Clock divider selection bits (bit 1 and 2 of the UART mode register

[Address: 002016]). Refer to Table 2.5.2.

Table 2.5.2 Clock divider selection for serial I/O

Clock divider

Clock divider selection bits

bit 2

bit 1

256

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