7630 datasheet(147/238 Pages) RENESAS

147 / 238 page

2-81

7630 Group User’s Manual

APPLICATION

2.5 Serial I/O

Fig. 2.5.20 Setting of related registers on transmitting side [Communication using UART]

USTS

UART status register [Address: 002316]

Transmission register empty flag :

This flag is set to “1” at transmit shift completed.

Check a completion of transmitting 1-word data with this flag.

Transmission buffer empty flag :

This flag is set to “1” at transfer data from the Transmit buffer

Check whether the next transmission data is writable to the

Transmit buffer register with this flag.

• Transmitting side

CPUM

CPU mode register [Address: 000016]

Internal system clock selection bit :

φ = f(XIN) divided by 2

(high-speed mode)

UMOD

UART mode register [Address: 002016]

Clock divider selection bits :

φ divided by 8

101

Stop bits selection bit : Two stop bits

Parity enable bit : Parity disabled

Word length selection bits : 8 bits

UCON

UART control register [Address: 002216]

Transmit enable bit : Transmit disabled

(Set this bit to “1” at starting communication.)

Receive enable bit : Receive disabled

Transmission initialization bit : Initialize the transmit enable bit and

transmit status register flags.

Receive initialization bit : No action

UBRG

UART baud rate generator [Address: 002116]

Set

Transfer bit rate ! 16 !

V The value p is decided by the Clock divider selection bits (bit 1 and bit 2

of the UART mode register [address: 002016]). Refer to Table 2.5.2.

– 1

7630 Datasheet(PDF) 147 Page - Renesas Technology Corp

7630 Datasheet(HTML) 147 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL