7630 datasheet(155/238 Pages) RENESAS

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7630 Group User’s Manual

APPLICATION

2.5 Serial I/O

Fig. 2.5.29 Control procedure on receiving side [Communication using UART]

RESET

Initialization

UMOD [Address: 002016]

CPUM [Address: 000016]

00000X002

100X101X2

X : These bits are not used in this application.

Please set these bits to “0” or “1” appropriately.

UCON [Address: 002216]

XXXX10002

•

φ = f(XIN) divided by 2 (high-speed mode)

UBRG [Address: 002116]

4 – 1

UCON [Address: 002216], bit 1

USTS [Address: 002316], bit 2?

• Check the completion of receiving with the Receive buffer full flag.

Read the received data

from URBR1 [Address: 002616]

and URBR2 [Address: 002716]

• Read the received 9 bits data.

The receive buffer full flag is cleared to “0” by reading data.

UCON [Address: 002216], bit 3

• Receive initialization (End of communication)

The Receive enable bit is cleared to “0”.

The Receive buffer full flag is set to “1”.

The Receive parity error flag is cleared to “0”.

The Receive framing error flag is cleared to “0”.

The Receive overrun flag is cleared to “0”.

The Receive error sum flag is cleared to “0”.

• Receive enable (Start of communication)

Output “L” from URTS.

• Receiving side

• Check the Receive error sum flag.

USTS [Address: 002316], bit 6?

Processing for error

• Transfer data format : 1ST-9DATA-2SP

• Receive initialization

The Receive enable bit is cleared to “0”.

The Receive buffer full flag is set to “1”.

The Receive parity error flag is cleared to “0”.

The Receive framing error flag is cleared to “0”.

The Receive overrun flag is cleared to “0”.

The Receive error sum flag is cleared to “0”.

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