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HC210 Datasheet(PDF) 5 Page - Altera Corporation |
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HC210 Datasheet(HTML) 5 Page - Altera Corporation |
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5 / 228 page ![]() Altera Corporation 1–3 September 2008 Preliminary Feature Overview The HardCopy II device family consists of five devices. Table 1–1 summarizes the features available in the HardCopy II devices. Table 1–1. HardCopy II Device Family Features Feature HC210W (1) HC210 HC220 HC230 HC240 ASIC equivalent gates (2) 1,000,000 1,000,000 1,900,000 2,900,000 3,600,000 M4K RAM blocks (4 Kbits plus parity) 190 190 408 614 768 (3) M-RAM blocks (512 Kbits plus parity) 0 026 9 Total RAM bits (including parity bits) 875,520 875,520 3,059,712 6,368,256 8,847,360 Enhanced PLLs 2 2 2 4 4 Fast PLLs 2 2 2 4 8 Maximum user I/O pins (4), (5) 308 334 494 698 951 Notes to Table 1–1: (1) HC210W devices are in a wire bond package. All other HardCopy II devices and Stratix II FPGAs use a flip-chip package. Devices in a wire bond package offer different performance and signal integrity characteristics compared to devices in a flip-chip package. (2) This is the number of ASIC equivalent gates available in the HardCopy II base array, shared between both adaptive logic module (ALM) logic and DSP functions from a Stratix II FPGA prototype. Each Stratix II adaptive logic module (ALM) is equal to approximately 30 ASIC equivalent gates. The number of ASIC equivalent gates usable is bounded by the number of ALMs in the companion Stratix II FPGA device. (3) Total number of usable M4K blocks is 768, which allows migration compatibility when prototyping with an EP2S180 device. This may be different from the Quartus II software total physical M4K count of the HC240. (4) The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs. (5) The Quartus II I/O pin counts include an additional pin ( PLLENA), which is not available as a general-purpose I/O pin. The PLLENA pin can only be used to enable the PLLs. |
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