HC210 datasheet(65/228 Pages) ALTERA

65 / 228 page

Altera Corporation

4–23

September 2008

Maximum Input Clock Rates

PCI-X (1)

500

—

500

—

500

—

500

MHz

Differential SSTL2 class I

(2), (3)

500

—

500

—

500

MHz

Differential SSTL2 class II

(2), (3)

500

—

500

—

500

MHz

Differential SSTL18 class I

(2), (3)

500

—

500

—

500

MHz

Differential SSTL18 class II

(2), (3)

500

—

500

—

500

MHz

1.8-V Differential HSTL

class I (2), (3)

500

—

500

—

500

MHz

1.8-V Differential HSTL

class II (2), (3)

500

—

500

—

500

MHz

1.5-V Differential HSTL

class I (2), (3)

500

—

500

—

500

MHz

1.5-V Differential HSTL

class II (2), (3)

500

—

500

—

500

MHz

LVDS

—

520

—

717

450

717

450

MHz

LVPECL

—

450

—

450

MHz

HyperTransport

—

520

—

717

—

717

—

MHz

Notes to Table 4–33:

(1)

The PCI clamping diode is only supported on the top and bottom I/O pins.

(2)

This I/O standard is only supported on the

DQS, CLK, and PLL_FB input pins.

(3)

For HC210 and HC220, differential HSTL/SSTL input is supported on top/bottom

PLL_FB, the top clock pins and

DQS pins located on the top I/Os.

Table 4–33. HardCopy II Maximum Input Clock Rates of HC210, HC220, HC230 and HC240 Devices (Part

2 of 2)

I/OStandard

Memory

Interface

IOEs

High

Speed

IOEs

General

Purpose

IOEs

CLK

[0..3,

8..11]

CLK

[4..7,

12..15]

FPLL_CLK

PLL_FB

Unit

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