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HC210 Datasheet(PDF) 89 Page - Altera Corporation |
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HC210 Datasheet(HTML) 89 Page - Altera Corporation |
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89 / 228 page  Altera Corporation 4–47 September 2008 Electrostatic Discharge Figure 4–3 shows a typical HardCopy II CMOS I/O buffer structure which will be used to explain ESD protection. Figure 4–3. Transistor-Level Diagram of HardCopy II Device I/O Buffers The CMOS output drivers in the I/O pins intrinsically provide electrostatic discharge protection. There are two cases to consider for ESD voltage strikes: positive voltage zap and negative voltage zap. A positive ESD voltage zap occurs when a positive voltage is present on an I/O pin due to an ESD charge event. This can cause the N+ (Drain)/PSubstrate junction of the N-channel drain to break down and the N+ (Drain)/P-Substrate/N+ (Source) intrinsic bipolar transistor turns on to discharge ESD current from I/O pin to GND. |
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