HC210 datasheet(64/228 Pages) ALTERA

64 / 228 page

4–22

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

Maximum Input

Clock Rates

Tables 4–33 and 4–34 show the maximum input clocking rates of

HardCopy II I/Os.

CCLKLR

Input capacitance on left/right clock

inputs CLK0, CLK2, CLK8, CLK10.

4.3

6.1

CCLKLR+

Input capacitance on left/right clock

inputs CLK1, CLK3, CLK9, and CLK11.

4.2

3.3

COUTFB

Input capacitance on dual-purpose clock

output/feedback pins in PLL banks 9, 10,

11, and 12.

6.9

6.7

Note to Table 4–32:

(1)

Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement

accuracy is within ± 0.5 pF.

Table 4–32. HardCopy II Device Capacitance

Note (1) (Part 2 of 2)

Symbol

Parameter

HC210W

Typical

HC210, HC220,

HC230, HC240

Typical

Unit

Table 4–33. HardCopy II Maximum Input Clock Rates of HC210, HC220, HC230 and HC240 Devices (Part

1 of 2)

I/OStandard

Memory

Interface

IOEs

High

Speed

IOEs

General

Purpose

IOEs

CLK

[0..3,

8..11]

CLK

[4..7,

12..15]

FPLL_CLK

PLL_FB

Unit

LVTTL

500

MHz

2.5 V

500

MHz

1.8 V

500

MHz

1.5 V

500

MHz

LVCMOS

500

MHz

SSTL2 class I

500

—

500

—

500

MHz

SSTL2 class II

500

—

500

—

500

MHz

SSTL18 class I

500

—

500

—

500

MHz

SSTL18 class II

500

—

500

—

500

MHz

1.5 V HSTL class I

500

—

500

—

500

MHz

1.5 V HSTL class II

500

—

500

—

500

MHz

1.8 V HSTL class I

500

—

500

—

500

MHz

1.8 V HSTL class II

500

—

500

—

500

MHz

PCI (1)

500

—

500

—

500

—

500

MHz

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