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HC210 Datasheet(PDF) 90 Page - Altera Corporation |
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HC210 Datasheet(HTML) 90 Page - Altera Corporation |
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90 / 228 page ![]() 4–48 Altera Corporation September 2008 HardCopy Series Handbook, Volume 1 The dashed line (see Figure 4–4) shows the ESD current discharge path during a positive ESD zap. Figure 4–4. ESD Protection During Positive Voltage Zap When the I/O pin receives a negative ESD zap at the pin that is less than -0.7 V (0.7 V is the voltage drop across a diode), the intrinsic P-Substrate/N+ drain diode is forward biased. Hence, the discharge ESD current path is from GND to the I/O pin, as shown in Figure 4–5. Figure 4–5. ESD Protection During Negative Voltage Zap |
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