HC210 datasheet(14/228 Pages) ALTERA

14 / 228 page

2–6

Altera Corporation

Preliminary

September 2008

HardCopy Series Handbook, Volume 1

HCells

HardCopy II devices are built using an array of fine-grained architecture

blocks called HCells. HCells are a collection of logic transistors based on

1.2 V, 90 nm process technology, similar to Stratix II devices. The

construction of logic using HCells allows flexible functionality such that

when HCells are combined, all viable logic combinations of Stratix II

functionality are replicated. These HCells constitute the array of HCells

area in Figure 2–1. Only HCells needed to implement the customer

design are assembled together, which optimizes HCell utilization. The

unused area of the HCell logic fabric is powered down, resulting in

significant power savings compared with the Stratix II FPGA prototype.

The Quartus II software uses the library of pre-characterized HCell

macros to place Stratix II ALM and DSP configurations into the

HardCopy II HCell-based logic fabric. An HCell macro defines how a

group of HCells are connected together within the array. HCell macros

can construct all combinations of combinational logic, adder, and register

functions that can be implemented by a Stratix II ALM. HCells not used

for ALM configurations can be used to implement DSP block functions.

Based on design requirements, the Quartus II software will chose the

appropriate HCell macros to implement the design functionality. For

example, Stratix II ALMs offer flexible look-up table (LUT) blocks,

registers, arithmetic blocks, and LAB-wide control signals. In

HardCopy II devices, if your design requires these architectural elements,

the Quartus II synthesis tool will map the design to the appropriate

HCells, resulting in improved design performance compared to the

Stratix II FPGA prototype.

Stratix II FPGAs have dedicated DSP blocks to implement various DSP

functions. Stratix II DSP blocks consist of a multiplier block, an

adder/subtractor/accumulator block, a summation block, input and

output interfaces, and input and output registers. In HardCopy II

devices, HCell macros implement Stratix II DSP block functionality with

area efficiency and performance on par with the dedicated DSP blocks in

Stratix II FPGAs.

There are eight HCell macros which implement the eight supported

modes of operation for the Stratix II DSP block:

■

9 × 9 multiplier

■

9 × 9 two-multiplier adder (9 × 9 complex multiply)

■

9 × 9 four-multiplier adder

■

18 × 18 multiplier

■

18 × 18 two-multiplier adder (18 × 18 complex multiply)

■

18 × 18 four-multiplier adder

■

52-bit (18 × 18) multiplier-accumulator

■

36 × 36 multiplier

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