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HC210 Datasheet(PDF) 86 Page - Altera Corporation

Part # HC210
Description  HardCopy II Device Family
PDF  228 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

HC210 Datasheet(HTML) 86 Page - Altera Corporation

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4–44
Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Table 4–48. DQS Phase Jitter Specifications for DLL-Delayed Clock (tDQS
PHASE_JITTER)
Note (1)
Number of DQS Delay Buffer
Stages (2)
DQS Phase Jitter
Unit
130
ps
260
ps
390
ps
4
120
ps
Notes to Table 4–48:
(1)
Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is caused
by DLL tracking).
(2)
Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
Table 4–49. DQS Phase-Shift Error Specifications for DLL-Delayed Clock
(tDQS_PSERR)
Note (1)
Number of DQS Delay Buffer
Stages (2))
HC210, HC220, HC230 HC240
Unit
130
ps
260
ps
390
ps
4
120
ps
Notes to Table 4–49:
(1)
This error specification is the absolute maximum and minimum error. For
example, skew on three delay buffer stages with an HC240 device is 105 ps or
±52.5ps.
(2)
Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.



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