HC210 datasheet(95/228 Pages) ALTERA

95 / 228 page

Altera Corporation

5–3

September 2008

HardCopy II Development Flow

■

HardCopy II Device Preliminary Timing

—The Quartus II software

performs a timing analysis of HardCopy II devices based on

preliminary timing models and Fitter placements. Final timing

results for HardCopy II devices are provided by the HardCopy

Design Center.

■

HardCopy II Handoff Report

-—The Quartus II software generates a

handoff report containing information about the HardCopy II design

used by the HardCopy Design Center in the design review process.

■

Formal Verification

—Cadence Encounter Conformal software can

now perform formal verification between the source RTL design files

and post-compile gate level netlist from a HardCopy II design.

HardCopy II

Development

Flow

In the Quartus II software, you have two methods for designing your

Stratix II FPGA and HardCopy II companion device together in one

Quartus II project.

■

Design the HardCopy II device first, and create the Stratix II FPGA

companion device second and build your prototype for in-system

verification

■

Design the Stratix II FPGA first and create a HardCopy II companion

device second

Both of these flows are illustrated at a high level in Figure 5–1. The added

features in the HardCopy II Utilities menu assist you in completing your

HardCopy II design for submission to Altera’s HardCopy Design Center

for back-end implementation.

HC210 Datasheet(PDF) 95 Page - Altera Corporation