HC210 datasheet(79/228 Pages) ALTERA

79 / 228 page

Altera Corporation

4–37

September 2008

HighSpeed I/O Specifications

Table 4–41 shows the high-speed I/O timing specifications for HC210,

HC220, HC230 and HC240 HardCopy II devices.

Output tRISE

All differential I/O standards

—

(5)

Output tFALL

All differential I/O standards

—

(5)

tDUTY

——

—

DPA run length

—

6,400

DPA jitter tolerance

(peak-to-peak)

——

—

(5)

——

DPA lock time

Standard

Training

Pattern

Transition

Density

—

Number of

repetitions

——

—

SPI4

0000000000

1111111111

10%

(5)

——

Parallel Rapid I/O

10010000

25%

(5)

——

—

10010000

50%

(5)

——

Miscellaneous

10101010

100%

(5)

——

—

10101010

—

(5)

——

Notes to Table 4–40:

(1)

These numbers are preliminary and pending further silicon characterization.

(2)

When J = 4 to 10, the SERDES block is used.

When J = 1 or 2, the SERDES block is bypassed.

(3)

The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150

≤ input

clock frequency × W

≤ 640.

(4)

The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and

the clock routing resource (global, regional, or local) used. The I/O differential buffer and input register do not

have a minimum toggle rate.

(5)

Contact the Altera Applications Group for more information.

Table 4–40. HardCopy II High-Speed I/O Specifications for HC210W Device Notes (1), (2) (Part 2 of 2)

Symbol

Conditions

Min

Typ

Max

Unit

Table 4–41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 1 of 2)

Symbol

Conditions

Min

Typ

Max

Unit

fHSCLK (clock frequency)

fHSCLK = fHSDR / W

W = 2 to 32 (LVDS, HyperTransport technology)

(2)

—

520

MHz

W = 1 (SERDES bypass, LVDS only)

—

500

MHz

W = 1 (SERDES used, LVDS only)

150

—

717

MHz

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