HC210 datasheet(27/228 Pages) ALTERA

27 / 228 page

Altera Corporation

2–19

September 2008

Preliminary

I/O Structure and Features

Figure 2–5. I/O Type Support in HC230 Devices

Notes (1), (2)

Bank 4

Memory Interface IOEs

PLL 5

PLL 11

Bank 11 Bank 9

Bank 7

Memory Interface IOEs

Bank 8

Memory Interface IOEs

I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/

LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V

HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards.

I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/

LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards.

Bank 3

Memory Interface IOEs

PLL 6

PLL 12

Bank 2

High-Speed IOEs

Bank 1

High-Speed IOEs

Bank 5

General-Purpose IOEs

Bank 6

General-Purpose IOEs

PLL 1

PLL 2

I/O Banks 5 & 6 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS

&1.5-V LVCMOS

I/O Banks 1 & 2 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V

LVCMOS, LVDS & HyperTransport Technology

Bank 12 Bank 10

PLL 7

PLL 8

CLK, PLL_FB input pins & PLL_OUT output

pins support differential SSTL, differential HSTL,

LVDS & HyperTransport technology. CLK & PLL_FB

pins support LVPECL. DQS input pins support

differential SSTL and differential HSTL I/O standards.

CLK, PLL_FB input pins, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST,

& PLL_OUT output

pins support differential SSTL, differential HSTL,

LVDS & HyperTransport technology. CLK & PLL_FB

pins support LVPECL. DQS input pins support

differential SSTL and differential HSTL I/O standards.

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