HC210 datasheet(80/228 Pages) ALTERA

80 / 228 page

4–38

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

fHSDR (data rate)

J = 4 to 10 (LVDS, HyperTransport technology)

150

—

1,040

Mbps

J = 2 (LVDS, HyperTransport technology)

(3)

—

760

Mbps

J = 1 (LVDS only)

(3)

—

500

Mbps

fHSDRDPA (DPA data rate)

J = 4 to 10 (LVDS, HyperTransport technology)

150

—

1,040

Mbps

TCCS

All differential standards

—

200

All differential standards

330

—

Output jitter

—

190

Output tRISE

All differential I/O standards

—

160

Output tFALL

All differential I/O standards

—

180

tDUTY

—45

DPA run length

—

6,400

DPA jitter tolerance

(peak-to-peak)

—0.44

—

DPA lock time

Standard

Training

Pattern

Transition

Density

—

Number of

repetitions

——

—

SPI4

0000000000

1111111111

10%

256

—

Parallel Rapid I/O

10010000

25%

256

—

10010000

50%

256

—

Miscellaneous

10101010

100%

256

—

10101010

—

256

—

Notes to Table 4–41:

(1)

When J = 4 to 10, the SERDES block is used.

When J = 1 or 2, the SERDES block is bypassed.

(2)

The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150

≤ input

clock frequency × W

≤ 1,040.

(3)

The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and

the clock routing resource (global, regional, or local) used. The I/O differential buffer and input register do not

have a minimum toggle rate.

Table 4–41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 2 of 2)

Symbol

Conditions

Min

Typ

Max

Unit

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