HC210 datasheet(76/228 Pages) ALTERA

76 / 228 page

4–34

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

1.5-V Differential

HSTL Class I (3)

OCT 50

550

—

550

MHz

Notes to Table 4–37:

(1)

The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology

on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from

0 to 5 pF.

(2)

CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table.

(3)

Like Stratix II devices, differential HSTL and SSTL is supported only on the column

CLK, PLL_OUT and memory

interface

DQS IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and

SSTL.

Table 4–37. HardCopy II Maximum Output Clock Rate for HC210, HC220, HC230 and HC240 Devices (OCT)

Note (1) (Part 2 of 2)

I/O Standard

Drive

Strength

Memory

Interface

IOEs

High

Speed

IOEs

General Purpose

IOEs

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT

Unit

Bottom

Column

Right

Row

Table 4–38. HardCopy II Maximum Output Clock Rate for HC210W using OCT

Notes (1), (4) (Part 1 of 2)

I/O Standard

Drive

Strength

Memory

Interface

IOEs

High

Speed

IOEs

General Purpose

IOEs

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT

Unit

Bottom

Column

Right

Row

3.3-V LVTTL

OCT 50

280

MHz

2.5-V LVTTL

OCT 50

245

MHz

1.8-V LVTTL

OCT 50

290

MHz

3.3-V LVCMOS

OCT 50

245

MHz

1.5-V LVCMOS

OCT 50

190

MHz

SSTL-2 Class I

OCT 50

280

—

280

MHz

SSTL-2 Class II

OCT 25

280

—

280

MHz

SSTL-18 Class I

OCT 50

230

—

230

MHz

SSTL-18 Class II OCT 25

220

—

220

MHz

1.5-V HSTL

Class I

OCT 50

190

—

190

MHz

1.8-V HSTL

Class I

OCT 50

270

—

270

MHz

1.8-V HSTL

Class II

OCT 50

210

—

210

MHz

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