HC210 datasheet(84/228 Pages) ALTERA

84 / 228 page

4–42

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

External

Memory

Interface

Specifications

Table 4–44 summarizes the maximum clock rate that HardCopy II devices

can support with external memory devices.

tARESET_RECONFIG Minimum pulse width on the areset signal

when using PLL reconfiguration. Reset the

PLL after scan done goes high.

500

—

Note to Table 4–43:

(1)

Limited by I/O fMAX.

Table 4–43. HardCopy II Fast PLL Specifications (Part 2 of 2)

Name

Description

Min

Typ

Max

Unit

Table 4–44. HardCopy II Maximum Clock Rate Support for External Memory Interfaces

Note (1)

Memory Standards

HardCopy II Device

Unit

Wire Bond Package

HC210W (2)

Flip Chip Package

HC210 / HC220 / HC230 / HC240 (3)

Com (C)

Ind (I)

Com (C)

Ind (I)

DDR

150

133

200

MHz

DDR2 (7)

150

133

267

233

MHz

QDRII (6)

150

133

250

233 (5)

MHz

RLDRAMII (6)

150

133

250 (4)

233 (4)

MHz

Notes to Table 4–44:

(1)

HardCopy II devices do not support PLL-based external memory interface except for SDR SDRAMs which do not

require the DLL.

(2)

HC210W supports memory interface on the top I/O banks.

(3)

HC210 and HC220 support memory interface on the top I/O banks. HC230 and HC240 support memory interface

on the top and bottom I/O banks.

(4)

You will need to under-clock a 300 MHz memory device.

(5)

You will need to under-clock a 250 MHz memory device.

(6)

Based on a DDIO scheme with the 1.8-V HSTL I/O standard.

(7)

Based on the PLL dedicated scheme. Use the same FMAX specification for Static-PHY and Auto-PHY since the

write-side is limited by the new tDS/tH specification.

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