HC210 datasheet(71/228 Pages) ALTERA

71 / 228 page

Altera Corporation

4–29

September 2008

Maximum Output Clock Rates

1.5-V differential

HSTL class II

(5)

16 mA

600

—

600

MHz

18 mA

600

—

600

MHz

20 mA (3)

650

—

650

MHz

Notes to Table 4–35:

(1)

The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology

on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from

0 to 5 pF.

(2)

CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and are excluded from this table.

(3)

This is the default setting in the Quartus® II software if supported by the pin location.

(4)

The PCI clamping diode is only supported on the top and bottom I/O pins.

(5)

Like Stratix II devices, differential HSTL and SSTL is supported only on the column

CLK, PLL_OUT and memory

interface

DQS IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and SSTL.

Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 5 of 5)

I/O Standard

Drive

Strength

Memory

Interface

IOEs

High

Speed

IOEs

General Purpose

IOEs

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT

Unit

Bottom

Column

Right

Row

Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices

Notes (1), (6) (Part 1 of 4)

I/O Standard

Drive

Strength

Memory

Interface

IOEs

High

Speed

IOEs

General Purpose

IOEs

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT

Unit

Bottom

Column

Right

Row

3.3-V LVTTL

4 mA

100

MHz

8 mA

170

MHz

12 mA

230

MHz

16 mA

240

—

240

MHz

20 mA

280

—

280

MHz

24 mA (3)

300

—

300

MHz

3.3-V LVCMOS

4 mA

175

MHz

8 mA

230

MHz

12 mA

260

—

260

MHz

16 mA

270

—

270

MHz

20 mA

290

—

290

MHz

24 mA (3)

310

—

310

MHz

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