HC210 datasheet(82/228 Pages) ALTERA

82 / 228 page

4–40

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

tLOCK

Time required for the PLL to lock

from the time it is enabled or the

end of device configuration

—0.03

tDLOCK

Time required for the PLL to lock

dynamically after automatic clock

switchover between two identical

clock frequencies

——

fSWITCHOVER

Frequency range where the clock

switchover performs properly

—

500

MHz

fCLKW

PLL closed loop bandwidth

0.13

1.2

16.9

MHz

fVCO

PLL VCO operating range for

HC210, HC220, HC230 and HC240

devices

300

—

1,040

MHz

PLL VCO operating range for

HC210W devices

300

—

840

MHz

fSS

Spread spectrum modulation

frequency

100

—

500

MHz

% spread

Percent down spread for a given

clock frequency

0.4

0.5

0.6

tPLL_PSERR

Accuracy of PLL phase shift

—

± 15

tARESET

Minimum pulse width on ARESET

signal.

10 (3)

——

500 (4)

——

tARESET_RECONFIG Minimum pulse width on the areset

signal when using PLL

reconfiguration. Reset the PLL after

scan done goes high.

500

—

Notes to Table 4–42:

(1)

Limited by I/O fMAX.

(2)

If the counter cascading feature of the PLL is used, there is no minimum output clock frequency.

(3)

Applicable when the PLL input clock has been running continuously for at least 10 µs.

(4)

Applicable when the PLL input clock has stopped toggling or has been running continuously for less than 10 µs.

Table 4–42. HardCopy II Enhanced PLL Specifications (Part 2 of 2)

Name

Description

Min

Typ

Max

Unit

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