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HC210 Datasheet(PDF) 63 Page - Altera Corporation |
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HC210 Datasheet(HTML) 63 Page - Altera Corporation |
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63 / 228 page ![]() Altera Corporation 4–21 September 2008 Pin Capacitance Pin Capacitance Table 4–32 shows the HardCopy II device family’s pin capacitance. Table 4–31. Series and Differential On-Chip Termination Specification for I/O Banks Supporting High-Speed and General Purpose IOEs Notes (1), (3), (4) Symbol Description Conditions Resistance Tolerance Commercial Max Industrial Max Unit 25 Ω RS 3.3/2.5 Internal series termination without calibration (25- Ω setting) VCCIO = 3.3/2.5 V ± 30 ± 30 % 50 Ω R S 3.3/2.5/1.8 Internal series termination without calibration (50- Ω setting) VCCIO = 3.3/2.5/1.8 V ± 30 ± 30 % 50 Ω R S 1.5 Internal series termination without calibration (50- Ω setting) VCCIO = 1.5 V ± 36 ± 36 % RD (2) Internal differential termination for LVDS or HyperTransport technology —± 20 ± 25 % Notes to Table 4–31: (1) For information on which I/O banks support high-speed IOEs, refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook. (2) RD is only supported on high-speed IOEs. (3) The resistance tolerances for calibrated SOCT and POCT are at the time of initial calibration. If the temperature or voltage changes over time, the tolerance may also change. (4) This table applies only to HC210, HC220, HC230, and HC240 devices. Table 4–32. HardCopy II Device Capacitance Note (1) (Part 1 of 2) Symbol Parameter HC210W Typical HC210, HC220, HC230, HC240 Typical Unit CGPIO Input capacitance on I/O pins in I/O banks supporting general-purpose IOEs. 5.7 5.0 pF CMIIO Input capacitance on I/O pins in I/O banks supporting memory interface IOEs. 5.7 5.0 pF CHSIO Input capacitance on I/O pins in I/O banks supporting high-speed IOEs. 7.2 6.1 pF CCLKTB Input capacitance on top/bottom clock input pins CLK[4..7] and CLK[12..15]. 6.0 6.0 pF |
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