HC210 datasheet(51/228 Pages) ALTERA

51 / 228 page

Altera Corporation

4–9

September 2008

I/O Standard Specifications

Table 4–11. 3.3-V LVDS I/O Specifications

Note (1)

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

VCCIO

Output and feedback pins in PLL

banks 9, 10, 11, and 12 (2)

—

3.135

3.3

3.465

VID

Input differential voltage swing

(single-ended)

—

100

350

900

VICM

Input common mode voltage

—

200

1,250

1,800

VOD

Output differential voltage

(single-ended)

RL = 100

250

—

710

VOCM

Output common mode voltage

RL = 100

0.84

—

1.570

Receiver differential input discrete

resistor (external to HardCopy II

devices)

—

100

110

Notes to Table 4–11:

(1)

Like Stratix II devices, 3.3-V LVDS is supported by the top and bottom clock input differential buffers, and by the

PLL clock output and feedback pins.

(2)

The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.

The PLL clock output and feedback differential buffers are powered by

VCC_PLLOUT. For differential clock output

and feedback operation, connect

VCC_PLLOUT to 3.3 V.

Table 4–12. LVPECL Specifications (Part 1 of 2)

Note (1)

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

VCCIO

I/O supply voltage for I/O

banks that support high-

speed IOEs (2)

—

3.135

3.3

3.465

VID (peak-

to-peak)

Input differential voltage

swing

(single-ended)

—

300

600

1,000

VICM

Input common mode

voltage

RL = 100

1.0

—

2.5

VOD

Output differential voltage

(single-ended)

RL = 100

525

—

970

VOCM

Output common mode

voltage

RL = 100

1.650

—

2.275

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