HC210 datasheet(38/228 Pages) ALTERA

38 / 228 page

3–2

Altera Corporation

Preliminary

September 2008

HardCopy Series Handbook, Volume 1

The BSDL files for HardCopy II devices are different from the

corresponding Stratix® II FPGAs. For more information, or to receive

BSDL files for IEEE Std. 1149.1- compliant Hardcopy II devices, visit the

Altera website at www.altera.com.

The HardCopy II device instruction register length is 10 bits and the

USERCODE register length is 32 bits. The USERCODE registers are not

reprogrammable and are mask-programmed. The designer can choose an

appropriate 32 bit sequence which will be programmed into the

USERCODE registers.

USERCODE

00 0000 0111

Selects the 32-bit

USERCODE

TDI and TDO pins, allowing the

USERCODE to be serially shifted out

TDO.

IDCODE

00 0000 0110

Selects the

IDCODE register and

places it between

TDI and TDO,

allowing the

IDCODE to be serially

shifted out of

TDO.

HIGHZ (1)

00 0000 1011

Places the 1-bit

BYPASS register

between the

TDI and TDO pins,

which allows the BST data to pass

synchronously through selected

devices to adjacent devices during

normal device operation, while

tri-stating all of the I/O pins.

CLAMP (1)

00 0000 1010

Places the 1-bit

BYPASS register

between the

TDI and TDO pins,

which allows the BST data to pass

synchronously through selected

devices to adjacent devices during

normal device operation while

holding I/O pins to a state defined by

the data in the boundary-scan

Note to Table 3–1:

(1)

Bus hold and weak pull-up resistor features override the high-impedance state of

HIGHZ, CLAMP, and EXTEST.

Table 3–1. HardCopy II JTAG Instructions (Part 2 of 2)

JTAG Instruction

Instruction Code

Description

HC210 Datasheet(PDF) 38 Page - Altera Corporation

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