HC210 datasheet(15/228 Pages) ALTERA

15 / 228 page

Altera Corporation

2–7

September 2008

Preliminary

HCells

Only HCells that are required to implement the design’s DSP functions

are enabled. HCells not needed for DSP functions can be used for ALM

configurations, which results in efficient logic usage. In addition to area

management, the placement of these HCell macros allows for optimized

routing and performance.

An example of efficient logic area usage can be seen when comparing the

18 × 18 multiplier implementation in Stratix II FPGAs using the dedicated

DSP block versus the implementation in HardCopy II devices using

HCells. If the Stratix II DSP function only calls for one 18 × 18 multiplier,

the other three 18 × 18 multipliers and the DSP block’s adder output block

are not used (Figure 2–2). In HardCopy II devices, the HCell-based logic

fabric that is not used for DSP functions can be used to implement other

combinational logic, adder, and register functions.

Figure 2–2. Stratix II DSP Block versus HardCopy II HCell 18 × 18-Bit Multiplier Implementation

HardCopy II devices support all Stratix II DSP configurations (9 × 9,

18 × 18, and 36 × 36 multipliers) and all Stratix II DSP block features, such

as dynamic sign controls, dynamic addition/subtraction, saturation,

rounding, and dynamic input shift registers, except for dynamic mode

switching.

Input

Registers

× 18

Multiplier

× 18

Multiplier

× 18

Multiplier

× 18

Multiplier

Input

Registers

Output

Registers

Output

Registers

Adder/

Subtractor/

Accumulator

Block

Input

Registers

× 18

Multiplier

Output

Registers

Used portions of the block

Unused portions of the block

Stratix II DSP Block

HardCopy II HCell-Based Logic Fabric

These elements are implemented

using HCell macros.

Unused logic area can

be used to perform other

logic functions.

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